791 lines
32 KiB
Python
791 lines
32 KiB
Python
#!/usr/bin/python
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# -*- coding: utf-8 -*-
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#
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# FillArea.py
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#
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# Copyright 2017 JS Reynaud <js.reynaud@gmail.com>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301, USA.
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from __future__ import print_function
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from pcbnew import *
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import sys
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import tempfile
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import shutil
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import os
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import random
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import pprint
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import wx
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from inspect import currentframe, getframeinfo
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import time
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def wxPrint(msg):
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wx.LogMessage(msg)
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#
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if sys.version[0] == '2': # maui
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None
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else:
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xrange = range
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"""
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# This script fills all areas of a specific net with Vias (Via Stitching)
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#
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#
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# Usage in pcbnew's python console:
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# First you neet to copy this file (named FillArea.py) in your kicad_plugins
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# directory (~/.kicad_plugins/ on Linux)
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# Launch pcbnew and open python console (last entry of Tools menu)
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# Then enter the following line (one by one, Hit enter after each)
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import FillArea
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FillArea.FillArea().Run()
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# Other example:
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# You can add modifications to parameters by adding functions calls:
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FillArea.FillArea().SetDebug().SetNetname("GND").SetStepMM(1.27).SetSizeMM(0.6).SetDrillMM(0.3).SetClearanceMM(0.2).Run()
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# with
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# SetDebug: Activate debug mode (print evolution of the board in ascii art)
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# SetNetname: Change the netname to consider for the filling
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# (default is /GND or fallback to GND)
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# SetStepMM: Change step between Via (in mm)
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# SetSizeMM: Change Via copper size (in mm)
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# SetDrillMM: Change Via drill hole size (in mm)
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# SetClearanceMM: Change clearance for Via (in mm)
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# You can also use it in command line. In this case, the first parameter is
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# the pcb file path. Default options are applied.
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"""
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class ViaObject:
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"""
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ViaObject holds all information of a single Via
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"""
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def __init__(self, x, y, pos_x, pos_y):
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self.X = x
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self.Y = y
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self.PosX = pos_x
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self.PosY = pos_y
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class FillArea:
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"""
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Automaticaly add via on area where there are no track/existing via,
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pads and keepout areas
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"""
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REASON_OK = 0
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REASON_NO_SIGNAL = 1
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REASON_OTHER_SIGNAL = 2
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REASON_KEEPOUT = 3
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REASON_TRACK = 4
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REASON_PAD = 5
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REASON_DRAWING = 6
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REASON_STEP = 7
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FILL_TYPE_RECTANGULAR = "Rectangular"
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FILL_TYPE_STAR = "Star"
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FILL_TYPE_CONCENTRIC = "Concentric"
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FILL_TYPE_OUTLINE = "Outline"
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FILL_TYPE_OUTLINE_NO_HOLES = "Outline (No Holes)"
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def __init__(self, filename=None):
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self.filename = None
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self.clearance = 0
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# Net name to use
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self.SetPCB(GetBoard())
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# Set the filename
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self.SetFile(filename)
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# Step between via
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self.SetStepMM(2.54)
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# Size of the via (diameter of copper)
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self.SetSizeMM(0.46)
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# Size of the drill (diameter)
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self.SetDrillMM(0.20)
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# Isolation between via and other elements
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# ie: radius from the border of the via
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self.SetClearanceMM(0.2)
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self.only_selected_area = False
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self.delete_vias = False
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if self.pcb is not None:
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for lnet in ["GND", "/GND"]:
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if self.pcb.FindNet(lnet) is not None:
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self.SetNetname(lnet)
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break
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self.netname = None
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self.debug = False
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self.random = False
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self.fill_type = self.FILL_TYPE_RECTANGULAR
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if self.netname is None:
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self.SetNetname("GND")
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self.tmp_dir = None
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self.parent_area = None
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self.pcb_group = None
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self.target_net = None
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def SetFile(self, filename):
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self.filename = filename
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if self.filename:
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self.SetPCB(LoadBoard(self.filename))
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def SetDebug(self):
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wxPrint("Set debug")
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self.debug = True
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return self
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def SetRandom(self, r):
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random.seed()
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self.random = r
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return self
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def SetType(self, type):
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self.fill_type = type
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return self
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def SetPCB(self, pcb):
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self.pcb = pcb
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if self.pcb is not None:
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self.pcb.BuildListOfNets()
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return self
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def SetNetname(self, netname):
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self.netname = netname # .upper()
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# wx.LogMessage(self.netname)
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return self
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def SetStepMM(self, s):
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self.step = float(FromMM(s))
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return self
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def SetSizeMM(self, s):
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self.size = float(FromMM(s))
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return self
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def SetDrillMM(self, s):
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self.drill = float(FromMM(s))
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return self
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def OnlyOnSelectedArea(self):
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self.only_selected_area = True
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return self
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def DeleteVias(self):
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self.delete_vias = True
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return self
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def SetClearanceMM(self, s):
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self.clearance = float(FromMM(s))
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return self
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def GetReasonSymbol(self, reason):
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if isinstance(reason, ViaObject):
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return "X"
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if reason == self.REASON_NO_SIGNAL:
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return " "
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if reason == self.REASON_OTHER_SIGNAL:
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return "O"
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if reason == self.REASON_KEEPOUT:
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return "K"
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if reason == self.REASON_TRACK:
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return "T"
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if reason == self.REASON_PAD:
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return "P"
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if reason == self.REASON_DRAWING:
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return "D"
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if reason == self.REASON_STEP:
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return "-"
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return str(reason)
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def PrintRect(self, rectangle):
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"""debuging tool
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Print board in ascii art
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"""
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print("_" * (len(rectangle)+2))
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for y in range(len(rectangle[0])):
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print("|", end='')
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for x in range(len(rectangle)):
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print("%s" % self.GetReasonSymbol(rectangle[x][y]), end='')
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print("|")
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print("_" * (len(rectangle)+2))
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print('''
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OK = 'X'
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NO_SIGNAL = ' '
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OTHER_SIGNAL = 'O'
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KEEPOUT = 'K'
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TRACK = 'T'
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PAD = 'P'
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DRAWING = 'D'
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STEP = '-'
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''')
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def AddVia(self, position, x, y):
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if self.parent_area:
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m = PCB_VIA(self.parent_area)
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m.SetPosition(VECTOR2I(position))
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if self.target_net is None:
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self.target_net = self.pcb.FindNet(self.netname)
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m.SetNet(self.target_net)
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m.SetViaType(VIATYPE_THROUGH)
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m.SetDrill(int(self.drill))
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m.SetWidth(int(self.size))
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m.SetIsFree(True)
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# again possible to mark via as own since no timestamp_t binding kicad v5.1.4
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# m.SetParentGroup(self.parent_group)
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# wx.LogMessage('adding vias')
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self.pcb.Add(m)
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self.pcb_group.AddItem(m)
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return m
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else:
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wxPrint("\nUnable to find a valid parent area (zone)")
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def RefillBoardAreas(self):
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for i in range(self.pcb.GetAreaCount()):
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area = self.pcb.GetArea(i)
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area.UnFill()
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filler = ZONE_FILLER(self.pcb)
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filler.Fill(self.pcb.Zones())
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def CheckViaInAllAreas(self, via, all_areas):
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'''
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Checks if an existing Via collides with another area
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'''
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# Enum all area
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for area in all_areas:
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area_layer = area.GetLayer()
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area_clearance = area.GetLocalClearance()
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area_priority = area.GetAssignedPriority()
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is_rules_area = area.GetIsRuleArea()
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is_rule_exclude_via_area = area.GetIsRuleArea() and area.GetDoNotAllowVias()
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is_target_net = (area.GetNetname() == self.netname) # (area.GetNetname().upper() == self.netname)
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# wx.LogMessage(area.GetNetname()) #wx.LogMessage(area.GetNetname().upper())
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if (not is_target_net or is_rule_exclude_via_area): # Only process areas that are not in the target net or is a rule area that could exlude vias
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# print("Process...")
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# Offset is half the size of the via plus the clearance of the via or the area
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offset = max(self.clearance, area_clearance) + self.size / 2
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for dx in [-offset, offset]:
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# All 4 corners of the via are testet (upper, lower, left, right) but not the center
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for dy in [-offset, offset]:
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point_to_test = wxPoint(via.PosX + dx, via.PosY + dy)
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# TODO: check all layers instead of GetFirstLayer
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hit_test_area = area.HitTestFilledArea(area.GetFirstLayer(), VECTOR2I(point_to_test)) # Collides with a filled area
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hit_test_edge = area.HitTestForEdge(VECTOR2I(point_to_test), 1) # Collides with an edge/corner
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try:
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hit_test_zone = area.HitTestInsideZone(VECTOR2I(point_to_test)) # Is inside a zone (e.g. KeepOut/Rules)
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except:
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hit_test_zone = False
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wxPrint('exception: missing HitTestInsideZone: To Be Fixed')
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# hit_test_zone = area.HitTest(point_to_test)
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# Is inside a zone (e.g. KeepOut/Rules with via exlusion) kicad
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if is_rule_exclude_via_area and (hit_test_area or hit_test_edge or hit_test_zone):
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return self.REASON_KEEPOUT # Collides with keepout/rules
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elif (hit_test_area or hit_test_edge) and not is_rules_area:
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# Collides with another signal (e.g. on another layer) but not a rule zone
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return self.REASON_OTHER_SIGNAL
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elif hit_test_zone and not is_rules_area:
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# Check if the zone is higher priority than other zones of the target net in the same point
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# target_areas_on_same_layer = filter(lambda x: ((x.GetPriority() > area_priority) and (x.GetLayer() == area_layer) and (x.GetNetname().upper() == self.netname)), all_areas)
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target_areas_on_same_layer = filter(lambda x: ((x.GetPriority() > area_priority) and (
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x.GetLayer() == area_layer) and (x.GetNetname() == self.netname)), all_areas)
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for area_with_higher_priority in target_areas_on_same_layer:
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if area_with_higher_priority.HitTestInsideZone(VECTOR2I(point_to_test)):
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break # Area of target net has higher priority on this layer
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else:
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# Collides with another signal (e.g. on another layer)
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return self.REASON_OTHER_SIGNAL
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return self.REASON_OK
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def ClearViaInStepSize(self, rectangle, x, y, distance):
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'''
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Stepsize==0
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O O O O O O O O O
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O O O O O O O O O
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O O O O O O O O O
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O O O O O O O O O
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O O O O O O O O O
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O O O O O O O O O
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O O O O O O O O O
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Standard
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O O O O O
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O O O O O
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O O O O O
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O O O O O
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Star
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O O O O O
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O O O O
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O O O O O
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O O O O
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O O O O O
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O O O O
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O O O O O
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'''
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for x_pos in range(x-distance, x+distance+1):
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if (x_pos >= 0) and (x_pos < len(rectangle)):
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# Star or Standard shape
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distance_y = distance-abs(x-x_pos) if self.fill_type == self.FILL_TYPE_STAR else distance
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for y_pos in range(y-distance_y, y+distance_y+1):
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if (y_pos >= 0) and (y_pos < len(rectangle[0])):
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if (x_pos == x) and (y_pos == y):
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continue
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rectangle[x_pos][y_pos] = self.REASON_STEP
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"""
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Check if vias would not overlap and if in same outline then apply at minimum 60% of self.step
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"""
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def CheckViaDistance(self, p, via, outline):
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p2 = VECTOR2I(via.GetPosition())
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dist = self.clearance + self.size/2 + via.GetWidth()/2
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# If via in same outline, then apply bigger space
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if outline.Collide(p2):
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dist = int(max(dist, self.step*0.6))
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return (p-p2).EuclideanNorm() >= dist
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"""
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Add via along outline (SHAPE_LINE_CHAIN), starting at offset (fraction between 0.0 and 1.0)
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Avoid placing vias to close to via present in all_vias
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"""
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def AddViasAlongOutline(self, outline, outline_parent, all_vias, offset=0):
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via_placed = 0
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step = max(self.step, self.size+self.clearance)
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len = int(outline.Length())
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steps = len // step
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steps = 1 if steps == 0 else steps
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stepsize = int(len//steps)
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for l in range(int(stepsize*offset), len, stepsize):
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p = outline.PointAlong(l)
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if all(self.CheckViaDistance(p, via, outline_parent) for via in all_vias):
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via = self.AddVia(p.getWxPoint(), 0, 0)
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all_vias.append(via)
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via_placed += 1
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return via_placed
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def ConcentricFillVias(self):
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wxPrint("Refill all zones")
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self.RefillBoardAreas()
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wxPrint("Calculate placement areas")
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zones = [zone for zone in self.pcb.Zones() if zone.GetNetname() == self.netname]
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self.parent_area = zones[0]
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# Create set of polygons where fill zones overlap on all layers
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poly_set = None
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for layer_id in self.pcb.GetEnabledLayers().CuStack():
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poly_set_layer = SHAPE_POLY_SET()
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for zone in zones:
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if zone.IsOnLayer(layer_id):
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if poly_set is not None or not self.only_selected_area or zone.IsSelected():
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poly_set_layer.Append(zone.RawPolysList(layer_id))
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if poly_set is None:
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poly_set = poly_set_layer
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else:
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poly_set.BooleanIntersection(poly_set_layer, SHAPE_POLY_SET.PM_FAST)
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poly_set.Simplify(SHAPE_POLY_SET.PM_FAST)
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if poly_set.OutlineCount() == 0:
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wxPrint("No areas to fill")
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return
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# Size the polygons so the vias fit inside
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poly_set.Inflate(int(-(1*self.clearance + 0.5*self.size)), 12, SHAPE_POLY_SET.CHAMFER_ALL_CORNERS)
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wxPrint("Generating concentric via placement")
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# Get all vias from the selected net
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all_vias = [track for track in self.pcb.GetTracks() if (track.GetClass() == "PCB_VIA" and track.GetNetname() == self.netname)]
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off = 0
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via_placed = 0
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# Place vias along all outlines and holes
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while poly_set.OutlineCount() > 0:
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for i in range(0, poly_set.OutlineCount()):
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outline = poly_set.Outline(i)
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via_placed += self.AddViasAlongOutline(outline, outline, all_vias, off)
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if self.fill_type != self.FILL_TYPE_OUTLINE_NO_HOLES:
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for k in range(0, poly_set.HoleCount(i)):
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hole = poly_set.Hole(i, k)
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via_placed += self.AddViasAlongOutline(hole, outline, all_vias, off)
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# Size the polygons to place the next ring
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if self.fill_type == self.FILL_TYPE_CONCENTRIC:
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poly_set.Inflate(int(-max(self.step, self.size+self.clearance)), 12, SHAPE_POLY_SET.CHAMFER_ALL_CORNERS)
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off = 0.5 if off == 0 else 0
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else:
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poly_set = SHAPE_POLY_SET()
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wxPrint("Refill all zones")
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self.RefillBoardAreas()
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msg = "{:d} vias placed\n".format(via_placed)
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wxPrint(msg+"Done!")
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return via_placed
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"""
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Main function which does the via placement or deletion
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"""
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def Run(self):
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VIA_GROUP_NAME = "ViaStitching {}".format(self.netname)
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if self.debug:
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print("Enumerate groups")
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for i in self.pcb.Groups():
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if i.GetName() == VIA_GROUP_NAME:
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if self.debug:
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print("Group {} Found !".format(VIA_GROUP_NAME))
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self.pcb_group = i
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"""
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Launch the process
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"""
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if self.delete_vias:
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# Do not perform a real delete since exposed function in python are not safe for deletion
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wx.MessageBox(
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"To delete vias:\n - select one of the generated via to select the group of vias named {}\n - hit delete key\n - That's all !".format(VIA_GROUP_NAME), "Information")
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"""
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if self.pcb_group is not None:
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all_vias = [track for track in self.pcb.GetTracks() if (track.GetClass() == "PCB_VIA" and track.GetNetname() == self.netname)]
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for via in all_vias:
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if via.GetParentGroup() is not None and via.GetParentGroup().GetName() == VIA_GROUP_NAME:
|
|
via.DeleteStructure()
|
|
|
|
"""
|
|
return # no need to run the rest of logic
|
|
|
|
if self.pcb_group is None:
|
|
self.pcb_group = PCB_GROUP(None)
|
|
self.pcb_group.SetName(VIA_GROUP_NAME)
|
|
self.pcb.Add(self.pcb_group)
|
|
|
|
if self.fill_type == self.FILL_TYPE_CONCENTRIC or self.fill_type == self.FILL_TYPE_OUTLINE or self.fill_type == self.FILL_TYPE_OUTLINE_NO_HOLES:
|
|
self.ConcentricFillVias()
|
|
if self.filename:
|
|
self.pcb.Save(self.filename)
|
|
|
|
return
|
|
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
target_tracks = self.pcb.GetTracks()
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
|
|
lboard = self.pcb.ComputeBoundingBox(False)
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
origin = lboard.GetPosition()
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
|
|
# Create an initial rectangle: all is set to "REASON_NO_SIGNAL"
|
|
# get a margin to avoid out of range
|
|
l_clearance = self.clearance + self.size
|
|
if l_clearance < self.step:
|
|
l_clearance = self.step
|
|
|
|
x_limit = int((lboard.GetWidth() + l_clearance) / l_clearance) + 1
|
|
y_limit = int((lboard.GetHeight() + l_clearance) / l_clearance) + 1
|
|
if self.debug:
|
|
print("l_clearance : {}; step : {}; size: {}; clearance: {}; x/y_limit ({} {}),board size : {} {}".format(l_clearance,
|
|
self.step,
|
|
self.size,
|
|
self.clearance,
|
|
x_limit,
|
|
y_limit,
|
|
lboard.GetWidth(),
|
|
lboard.GetHeight()))
|
|
rectangle = [[self.REASON_NO_SIGNAL]*y_limit for i in xrange(x_limit)]
|
|
|
|
if self.debug:
|
|
print("\nInitial rectangle:")
|
|
self.PrintRect(rectangle)
|
|
|
|
all_pads = self.pcb.GetPads()
|
|
all_tracks = self.pcb.GetTracks()
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
try:
|
|
all_drawings = filter(lambda x: x.GetClass() == 'PTEXT' and self.pcb.GetLayerID(
|
|
x.GetLayerName()) in (F_Cu, B_Cu), self.pcb.DrawingsList())
|
|
except:
|
|
all_drawings = filter(lambda x: x.GetClass() == 'PTEXT' and self.pcb.GetLayerID(
|
|
x.GetLayerName()) in (F_Cu, B_Cu), self.pcb.Drawings())
|
|
# wxPrint("exception on missing BOARD.DrawingsList")
|
|
all_areas = [self.pcb.GetArea(i) for i in xrange(self.pcb.GetAreaCount())]
|
|
# target_areas = filter(lambda x: (x.GetNetname().upper() == self.netname), all_areas) # KeepOuts are filtered because they have no name
|
|
# KeepOuts are filtered because they have no name
|
|
target_areas = filter(lambda x: (x.GetNetname() == self.netname), all_areas)
|
|
|
|
# Get the board outline and size with
|
|
board_edge = SHAPE_POLY_SET()
|
|
self.pcb.GetBoardPolygonOutlines(board_edge)
|
|
b_clearance = max(self.pcb.GetDesignSettings().m_CopperEdgeClearance, self.clearance) + self.size
|
|
board_edge.Deflate(int(b_clearance), int(12), SHAPE_POLY_SET.ROUND_ALL_CORNERS)
|
|
|
|
via_list = [] # Create a list of existing vias => faster than scanning through the whole rectangle
|
|
max_target_area_clearance = 0
|
|
|
|
# Enum all target areas (Search possible positions for vias on the target net)
|
|
for area in target_areas:
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
wxPrint("Processing Target Area: %s, LayerName: %s..." % (area.GetNetname(), area.GetLayerName()))
|
|
if self.parent_area is None:
|
|
self.parent_area = area
|
|
is_selected_area = area.IsSelected()
|
|
area_clearance = area.GetLocalClearance()
|
|
if max_target_area_clearance < area_clearance:
|
|
max_target_area_clearance = area_clearance
|
|
|
|
if (not self.only_selected_area) or (self.only_selected_area and is_selected_area): # All areas or only the selected area
|
|
# Check every possible point in the virtual coordinate system
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
for x in xrange(len(rectangle)):
|
|
if x % 10 == 0:
|
|
if self.debug:
|
|
print("%s: Line %u (x=%s;%s)" % (time.time(), currentframe().f_lineno, x, len(rectangle)))
|
|
for y in xrange(len(rectangle[0])):
|
|
# No other "target area" found yet => go on with processing
|
|
if rectangle[x][y] == self.REASON_NO_SIGNAL:
|
|
current_x = origin.x + (x * l_clearance) # Center of the via
|
|
current_y = origin.y + (y * l_clearance)
|
|
|
|
test_result = True # Start with true, if a check fails, it is set to false
|
|
|
|
# Offset is half the size of the via plus the clearance of the via or the area
|
|
offset = 0 # Use an exact zone match
|
|
point_to_test = wxPoint(int(current_x), int(current_y))
|
|
hit_test_area = area.HitTestFilledArea(
|
|
area.GetLayer(), VECTOR2I(point_to_test), int(offset)) # Collides with a filled area
|
|
# Collides with an edge/corner
|
|
hit_test_edge = area.HitTestForEdge(VECTOR2I(point_to_test), int(max(area_clearance, offset)))
|
|
# test_result only remains true if the via is inside an area and not on an edge
|
|
test_result = (hit_test_area and not hit_test_edge)
|
|
|
|
test_result = (test_result and board_edge.Collide(VECTOR2I(point_to_test))) # check if inside board outline
|
|
|
|
if test_result:
|
|
# Create a via object with information about the via and place it in the rectangle
|
|
via_obj = ViaObject(x=x, y=y, pos_x=current_x, pos_y=current_y)
|
|
rectangle[x][y] = via_obj
|
|
via_list.append(via_obj)
|
|
|
|
if self.debug:
|
|
print("\nPost target areas:")
|
|
self.PrintRect(rectangle)
|
|
|
|
# Enum all vias
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
wxPrint("Processing all vias of target area...")
|
|
for via in via_list:
|
|
reason = self.CheckViaInAllAreas(via, all_areas)
|
|
if reason != self.REASON_OK:
|
|
rectangle[via.X][via.Y] = reason
|
|
|
|
if self.debug:
|
|
print("\nPost areas:")
|
|
self.PrintRect(rectangle)
|
|
|
|
# Same job with all pads => all pads on all layers
|
|
wxPrint("Processing all pads...")
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
for pad in all_pads:
|
|
local_offset = max(pad.GetLocalClearance(), self.clearance, max_target_area_clearance) + (self.size / 2)
|
|
max_size = max(pad.GetSize().x, pad.GetSize().y)
|
|
|
|
start_x = int(floor(((pad.GetPosition().x - (max_size / 2.0 + local_offset)) - origin.x) / l_clearance))
|
|
stop_x = int(ceil(((pad.GetPosition().x + (max_size / 2.0 + local_offset)) - origin.x) / l_clearance))
|
|
|
|
start_y = int(floor(((pad.GetPosition().y - (max_size / 2.0 + local_offset)) - origin.y) / l_clearance))
|
|
stop_y = int(ceil(((pad.GetPosition().y + (max_size / 2.0 + local_offset)) - origin.y) / l_clearance))
|
|
|
|
for x in range(start_x, stop_x + 1):
|
|
for y in range(start_y, stop_y + 1):
|
|
try:
|
|
if isinstance(rectangle[x][y], ViaObject):
|
|
start_rect = wxPoint(origin.x + (l_clearance * x) - local_offset,
|
|
origin.y + (l_clearance * y) - local_offset)
|
|
size_rect = wxSize(2 * local_offset, 2 * local_offset)
|
|
if pad.HitTest(EDA_RECT(start_rect, size_rect), False):
|
|
rectangle[x][y] = self.REASON_PAD
|
|
else:
|
|
# Hit test doesn't handle large pads. This following should fix that.
|
|
m = PCB_VIA(self.parent_area)
|
|
m.SetPosition(wxPoint(origin.x + (l_clearance * x), origin.y + (l_clearance * y)))
|
|
m.SetNet(self.target_net)
|
|
m.SetViaType(VIATYPE_THROUGH)
|
|
m.SetDrill(int(self.drill))
|
|
m.SetWidth(int(self.size))
|
|
if pad.GetEffectivePolygon().Collide(m.GetEffectiveShape()):
|
|
rectangle[x][y] = self.REASON_PAD
|
|
|
|
except:
|
|
wxPrint("exception on Processing all pads...")
|
|
if self.debug:
|
|
print("\nPost pads:")
|
|
self.PrintRect(rectangle)
|
|
|
|
# Same job with tracks => all tracks on all layers
|
|
wxPrint("Processing all tracks...")
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
for track in all_tracks:
|
|
start_x = track.GetStart().x
|
|
start_y = track.GetStart().y
|
|
|
|
stop_x = track.GetEnd().x
|
|
stop_y = track.GetEnd().y
|
|
|
|
if start_x > stop_x:
|
|
d = stop_x
|
|
stop_x = start_x
|
|
start_x = d
|
|
|
|
if start_y > stop_y:
|
|
d = stop_y
|
|
stop_y = start_y
|
|
start_y = d
|
|
|
|
osx = start_x
|
|
osy = start_y
|
|
opx = stop_x
|
|
opy = stop_y
|
|
|
|
clearance = max(track.GetLocalClearance(""), self.clearance, max_target_area_clearance) + \
|
|
(self.size / 2) + (track.GetWidth() / 2)
|
|
|
|
start_x = int(floor(((start_x - clearance) - origin.x) / l_clearance))
|
|
stop_x = int(ceil(((stop_x + clearance) - origin.x) / l_clearance))
|
|
|
|
start_y = int(floor(((start_y - clearance) - origin.y) / l_clearance))
|
|
stop_y = int(ceil(((stop_y + clearance) - origin.y) / l_clearance))
|
|
|
|
for x in range(start_x, stop_x + 1):
|
|
for y in range(start_y, stop_y + 1):
|
|
try:
|
|
if isinstance(rectangle[x][y], ViaObject):
|
|
start_rect = wxPoint(origin.x + (l_clearance * x) - clearance,
|
|
origin.y + (l_clearance * y) - clearance)
|
|
size_rect = wxSize(2 * clearance, 2 * clearance)
|
|
if track.HitTest(EDA_RECT(start_rect, size_rect), False):
|
|
rectangle[x][y] = self.REASON_TRACK
|
|
except:
|
|
wxPrint("exception on Processing all tracks...")
|
|
|
|
if self.debug:
|
|
print("\nPost tracks:")
|
|
self.PrintRect(rectangle)
|
|
|
|
# Same job with existing text
|
|
wxPrint("Processing all existing drawings...")
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
for draw in all_drawings:
|
|
inter = float(self.clearance + self.size) / 2
|
|
bbox = draw.GetBoundingBox()
|
|
|
|
start_x = int(floor(((bbox.GetPosition().x - inter) - origin.x) / l_clearance))
|
|
stop_x = int(ceil(((bbox.GetPosition().x + (bbox.GetSize().x + inter)) - origin.x) / l_clearance))
|
|
|
|
start_y = int(floor(((bbox.GetPosition().y - inter) - origin.y) / l_clearance))
|
|
stop_y = int(ceil(((bbox.GetPosition().y + (bbox.GetSize().y + inter)) - origin.y) / l_clearance))
|
|
|
|
for x in range(start_x, stop_x):
|
|
for y in range(start_y, stop_y):
|
|
rectangle[x][y] = self.REASON_DRAWING
|
|
|
|
if self.debug:
|
|
print("Post Drawnings:")
|
|
self.PrintRect(rectangle)
|
|
|
|
clear_distance = 0
|
|
if self.step != 0.0 and self.fill_type == self.FILL_TYPE_STAR:
|
|
# How much "via steps" should be removed around a via (round up)
|
|
clear_distance = int((self.step+l_clearance) / l_clearance)
|
|
|
|
via_placed = 0
|
|
for x in xrange(len(rectangle)):
|
|
for y in xrange(len(rectangle[0])):
|
|
if isinstance(rectangle[x][y], ViaObject):
|
|
if clear_distance:
|
|
self.ClearViaInStepSize(rectangle, x, y, clear_distance)
|
|
|
|
via = rectangle[x][y]
|
|
ran_x = 0
|
|
ran_y = 0
|
|
|
|
if self.random:
|
|
ran_x = (random.random() * l_clearance / 2.0) - (l_clearance / 4.0)
|
|
ran_y = (random.random() * l_clearance / 2.0) - (l_clearance / 4.0)
|
|
|
|
self.AddVia(wxPoint(via.PosX + ran_x, via.PosY + ran_y), via.X, via.Y)
|
|
via_placed += 1
|
|
|
|
if self.debug:
|
|
print("\nFinal result:")
|
|
self.PrintRect(rectangle)
|
|
|
|
if self.debug:
|
|
print("%s: Line %u" % (time.time(), currentframe().f_lineno))
|
|
self.RefillBoardAreas()
|
|
|
|
if self.filename:
|
|
self.pcb.Save(self.filename)
|
|
msg = "{:d} vias placed\n".format(via_placed)
|
|
wxPrint(msg+"Done!")
|
|
|
|
|
|
if __name__ == '__main__':
|
|
if len(sys.argv) < 2:
|
|
print("Usage: %s <KiCad pcb filename>" % sys.argv[0])
|
|
else:
|
|
import sys
|
|
FillArea(sys.argv[1]).SetDebug().Run()
|