test/kicad-action-scripts
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Porting to via creation in master branch (target: v6)

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Know issues

 - Unable to delete VIA (since The old method - used in 5.1 - don't
   work anymore)
 - Via are invisible after plugin run. Need to save and reopen file to
   see them
This commit is contained in:
Jean-Samuel Reynaud
2021-02-01 12:27:34 +01:00
parent 176bc80599
commit c863e5e6a8
3 changed files with 42 additions and 23 deletions
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53
ViaStitching/FillArea.py
View File

@ -134,6 +134,7 @@ class FillArea:
self.SetNetname("GND")
self.tmp_dir = None
self.parent_area = None
def SetFile(self, filename):
self.filename = filename
@ -232,16 +233,20 @@ STEP = '-'
''')
def AddVia(self, position, x, y):
m = VIA(self.pcb)
m.SetPosition(position)
m.SetNet(self.pcb.FindNet(self.netname))
m.SetViaType(VIA_THROUGH)
m.SetDrill(int(self.drill))
m.SetWidth(int(self.size))
# again possible to mark via as own since no timestamp_t binding kicad v5.1.4
m.SetTimeStamp(33) # USE 33 as timestamp to mark this via as generated by this script
#wx.LogMessage('adding vias')
self.pcb.Add(m)
if self.parent_area:
m = VIA(self.parent_area)
m.SetPosition(position)
m.SetNet(self.pcb.FindNet(self.netname))
m.SetViaType(VIATYPE_THROUGH)
m.SetDrill(int(self.drill))
m.SetWidth(int(self.size))
m.SetIsFree(True)
# again possible to mark via as own since no timestamp_t binding kicad v5.1.4
# m.SetParentGroup(self.parent_group)
#wx.LogMessage('adding vias')
self.pcb.Add(m)
else:
wxPrint("\nUnable to find a valid parent area (zone)")
def RefillBoardAreas(self):
for i in range(self.pcb.GetAreaCount()):
@ -258,9 +263,9 @@ STEP = '-'
# Enum all area
for area in all_areas:
area_layer = area.GetLayer()
area_clearance = area.GetClearance()
area_clearance = area.GetLocalClearance()
area_priority = area.GetPriority()
is_keepout_area = area.GetIsKeepout()
is_keepout_area = False # area.GetIsKeepout()
is_target_net = (area.GetNetname() == self.netname) # (area.GetNetname().upper() == self.netname)
# wx.LogMessage(area.GetNetname()) #wx.LogMessage(area.GetNetname().upper())
@ -272,7 +277,7 @@ STEP = '-'
for dy in [-offset, offset]:
point_to_test = wxPoint(via.PosX + dx, via.PosY + dy)
hit_test_area = area.HitTestFilledArea(point_to_test) # Collides with a filled area
hit_test_area = area.HitTestFilledArea(area.GetLayer(), point_to_test) # Collides with a filled area
hit_test_edge = area.HitTestForEdge(point_to_test, 1) # Collides with an edge/corner
try:
hit_test_zone = area.HitTestInsideZone(point_to_test) # Is inside a zone (e.g. KeepOut)
@ -350,11 +355,13 @@ STEP = '-'
#target_tracks = filter(lambda x: (x.GetNetname().upper() == self.netname), self.pcb.GetTracks())
target_tracks = filter(lambda x: (x.GetNetname() == self.netname), self.pcb.GetTracks())
target_tracks_cp = list(target_tracks)
l = len (target_tracks_cp)
l = len(target_tracks_cp)
for i in range(l):
if target_tracks_cp[i].Type() == PCB_VIA_T:
if target_tracks_cp[i].GetTimeStamp() == 33:
self.pcb.RemoveNative(target_tracks_cp[i])
# TODO: timestamp is no more available: looking for a better solution...
# if target_tracks_cp[i].GetTimeStamp() == 33:
# self.pcb.RemoveNative(target_tracks_cp[i])
None
self.RefillBoardAreas()
return # no need to run the rest of logic
@ -389,9 +396,10 @@ STEP = '-'
# Enum all target areas (Search possible positions for vias on the target net)
for area in target_areas:
wxPrint("Processing Target Area: %s, LayerName: %s..." % (area.GetNetname(), area.GetLayerName()))
if self.parent_area is None:
self.parent_area = area
is_selected_area = area.IsSelected()
area_clearance = area.GetClearance()
area_clearance = area.GetLocalClearance()
if max_target_area_clearance < area_clearance:
max_target_area_clearance = area_clearance
@ -412,10 +420,10 @@ STEP = '-'
# All 4 corners of the via are testet (upper, lower, left, right) but not the center
for dy in [-offset, offset]:
point_to_test = wxPoint(current_x + dx, current_y + dy)
hit_test_area = area.HitTestFilledArea(point_to_test) # Collides with a filled area
hit_test_area = area.HitTestFilledArea(
area.GetLayer(), point_to_test) # Collides with a filled area
# Collides with an edge/corner
hit_test_edge = area.HitTestForEdge(point_to_test, area_clearance)
# test_result only remains true if the via is inside an area and not on an edge
test_result &= (hit_test_area and not hit_test_edge)
@ -443,7 +451,7 @@ STEP = '-'
# Same job with all pads => all pads on all layers
wxPrint("Processing all pads...")
for pad in all_pads:
local_offset = max(pad.GetClearance(), self.clearance, max_target_area_clearance) + (self.size / 2)
local_offset = max(pad.GetLocalClearance(), self.clearance, max_target_area_clearance) + (self.size / 2)
max_size = max(pad.GetSize().x, pad.GetSize().y)
start_x = int(floor(((pad.GetPosition().x - (max_size / 2.0 + local_offset)) - origin.x) / l_clearance))
@ -491,7 +499,8 @@ STEP = '-'
opx = stop_x
opy = stop_y
clearance = max(track.GetClearance(), self.clearance, max_target_area_clearance) + (self.size / 2) + (track.GetWidth() / 2)
clearance = max(track.GetLocalClearance(""), self.clearance, max_target_area_clearance) + \
(self.size / 2) + (track.GetWidth() / 2)
start_x = int(floor(((start_x - clearance) - origin.x) / l_clearance))
stop_x = int(ceil(((stop_x + clearance) - origin.x) / l_clearance))

2
ViaStitching/FillAreaAction.py
View File

@ -65,7 +65,7 @@ class FillAreaAction(pcbnew.ActionPlugin):
self.boardDesignSettings = self.board.GetDesignSettings()
a.m_SizeMM.SetValue(str(pcbnew.ToMM(self.boardDesignSettings.GetCurrentViaSize())))
a.m_DrillMM.SetValue(str(pcbnew.ToMM(self.boardDesignSettings.GetCurrentViaDrill())))
a.m_ClearanceMM.SetValue(str(pcbnew.ToMM(self.boardDesignSettings.GetDefault().GetClearance())))
a.m_ClearanceMM.SetValue(str(pcbnew.ToMM(self.boardDesignSettings.GetSmallestClearanceValue())))
a.SetMinSize(a.GetSize())
PopulateNets("GND", a)