test/kicad-action-scripts
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k 5.14 compatibility (py2&3)

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Fix compatibilty issues with:
KiCAD 5.1.4
Py2
Py3
Added Net Combo box
Added button icon image
This commit is contained in:
easyw
2019-09-26 23:34:59 +02:00
parent c3f4dfbc25
commit 8c29a5f573
6 changed files with 239 additions and 58 deletions
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76
ViaStitching/FillArea.py Executable file → Normal file
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@ -28,6 +28,16 @@ import shutil
import os
import random
import pprint
import wx
def wxPrint(msg):
wx.LogMessage(msg)
#
if sys.version[0] == '2': #maui
xrange
else:
xrange = range
"""
# This script fills all areas of a specific net with Vias (Via Stitching)
@ -126,7 +136,7 @@ class FillArea:
self.SetPCB(LoadBoard(self.filename))
def SetDebug(self):
print("Set debug")
wxPrint("Set debug")
self.debug = True
return self
@ -146,7 +156,8 @@ class FillArea:
return self
def SetNetname(self, netname):
self.netname = netname.upper()
self.netname = netname #.upper()
#wx.LogMessage(self.netname)
return self
def SetStepMM(self, s):
@ -222,8 +233,9 @@ STEP = '-'
m.SetViaType(VIA_THROUGH)
m.SetDrill(int(self.drill))
m.SetWidth(int(self.size))
# No more possible to mark via as own since no timestamp_t binding
#m.SetTimeStamp(33) # USE 33 as timestamp to mark this via as generated
# again possible to mark via as own since no timestamp_t binding kicad v5.1.4
m.SetTimeStamp(33) # USE 33 as timestamp to mark this via as generated by this script
#wx.LogMessage('adding vias')
self.pcb.Add(m)
def RefillBoardAreas(self):
@ -244,7 +256,8 @@ STEP = '-'
area_clearance = area.GetClearance()
area_priority = area.GetPriority()
is_keepout_area = area.GetIsKeepout()
is_target_net = (area.GetNetname().upper() == self.netname)
is_target_net = (area.GetNetname() == self.netname) #(area.GetNetname().upper() == self.netname)
wx.LogMessage(area.GetNetname()) #wx.LogMessage(area.GetNetname().upper())
if (not is_target_net): # Only process areas that are not in the target net
offset = max(self.clearance, area_clearance) + self.size / 2 # Offset is half the size of the via plus the clearance of the via or the area
@ -253,7 +266,7 @@ STEP = '-'
point_to_test = wxPoint(via.PosX + dx, via.PosY + dy)
hit_test_area = area.HitTestFilledArea(point_to_test) # Collides with a filled area
hit_test_edge = area.HitTestForEdge(point_to_test) # Collides with an edge/corner
hit_test_edge = area.HitTestForEdge(point_to_test,1) # Collides with an edge/corner
hit_test_zone = area.HitTestInsideZone(point_to_test) # Is inside a zone (e.g. KeepOut)
if is_keepout_area and (hit_test_area or hit_test_edge or hit_test_zone):
@ -264,7 +277,8 @@ STEP = '-'
elif hit_test_zone:
# Check if the zone is higher priority than other zones of the target net in the same point
target_areas_on_same_layer = filter(lambda x: ((x.GetPriority() > area_priority) and (x.GetLayer() == area_layer) and (x.GetNetname().upper() == self.netname)), all_areas)
#target_areas_on_same_layer = filter(lambda x: ((x.GetPriority() > area_priority) and (x.GetLayer() == area_layer) and (x.GetNetname().upper() == self.netname)), all_areas)
target_areas_on_same_layer = filter(lambda x: ((x.GetPriority() > area_priority) and (x.GetLayer() == area_layer) and (x.GetNetname() == self.netname)), all_areas)
for area_with_higher_priority in target_areas_on_same_layer:
if area_with_higher_priority.HitTestInsideZone(point_to_test):
break # Area of target net has higher priority on this layer
@ -318,15 +332,16 @@ STEP = '-'
target_tracks = self.pcb.GetTracks()
if self.delete_vias:
# timestmap no more available
# target_tracks = filter(lambda x: (x.GetNetname().upper() == self.netname), self.pcb.GetTracks())
# for via in target_tracks:
# pprint.pprint(via.GetTimeStamp())
# if via.Type() == PCB_VIA_T:
# if via.GetTimeStamp() == 33:
# self.pcb.RemoveNative(via)
# self.RefillBoardAreas()
return # no need to run the rest of logic
# timestmap again available
#target_tracks = filter(lambda x: (x.GetNetname().upper() == self.netname), self.pcb.GetTracks())
target_tracks = filter(lambda x: (x.GetNetname() == self.netname), self.pcb.GetTracks())
for via in target_tracks:
#pprint.pprint(via.GetTimeStamp())
if via.Type() == PCB_VIA_T:
if via.GetTimeStamp() == 33:
self.pcb.RemoveNative(via)
self.RefillBoardAreas()
return # no need to run the rest of logic
lboard = self.pcb.ComputeBoundingBox(True)
origin = lboard.GetPosition()
@ -343,14 +358,15 @@ STEP = '-'
all_tracks = self.pcb.GetTracks()
all_drawings = filter(lambda x: x.GetClass() == 'PTEXT' and self.pcb.GetLayerID(x.GetLayerName()) in (F_Cu, B_Cu), self.pcb.DrawingsList())
all_areas = [self.pcb.GetArea(i) for i in xrange(self.pcb.GetAreaCount())]
target_areas = filter(lambda x: (x.GetNetname().upper() == self.netname), all_areas) # KeepOuts are filtered because they have no name
#target_areas = filter(lambda x: (x.GetNetname().upper() == self.netname), all_areas) # KeepOuts are filtered because they have no name
target_areas = filter(lambda x: (x.GetNetname() == self.netname), all_areas) # KeepOuts are filtered because they have no name
via_list = [] # Create a list of existing vias => faster than scanning through the whole rectangle
max_target_area_clearance = 0
# Enum all target areas (Search possible positions for vias on the target net)
for area in target_areas:
print ("Processing Target Area: %s, LayerName: %s..." % (area.GetNetname(), area.GetLayerName()))
wxPrint ("Processing Target Area: %s, LayerName: %s..." % (area.GetNetname(), area.GetLayerName()))
is_selected_area = area.IsSelected()
area_clearance = area.GetClearance()
@ -381,22 +397,22 @@ STEP = '-'
via_list.append(via_obj)
if self.debug:
print("\nPost target areas:")
wxPrint("\nPost target areas:")
self.PrintRect(rectangle)
# Enum all vias
print ("Processing all vias of target area...")
wxPrint ("Processing all vias of target area...")
for via in via_list:
reason = self.CheckViaInAllAreas(via, all_areas)
if reason != self.REASON_OK:
rectangle[via.X][via.Y] = reason
if self.debug:
print("\nPost areas:")
wxPrint("\nPost areas:")
self.PrintRect(rectangle)
# Same job with all pads => all pads on all layers
print ("Processing all pads...")
wxPrint ("Processing all pads...")
for pad in all_pads:
local_offset = max(pad.GetClearance(), self.clearance, max_target_area_clearance) + (self.size / 2)
max_size = max(pad.GetSize().x, pad.GetSize().y)
@ -417,11 +433,11 @@ STEP = '-'
rectangle[x][y] = self.REASON_PAD
if self.debug:
print("\nPost pads:")
wxPrint("\nPost pads:")
self.PrintRect(rectangle)
# Same job with tracks => all tracks on all layers
print ("Processing all tracks...")
wxPrint ("Processing all tracks...")
for track in all_tracks:
start_x = track.GetStart().x
start_y = track.GetStart().y
@ -462,11 +478,11 @@ STEP = '-'
rectangle[x][y] = self.REASON_TRACK
if self.debug:
print("\nPost tracks:")
wxPrint("\nPost tracks:")
self.PrintRect(rectangle)
# Same job with existing text
print ("Processing all existing drawings...")
wxPrint ("Processing all existing drawings...")
for draw in all_drawings:
inter = float(self.clearance + self.size)
bbox = draw.GetBoundingBox()
@ -482,10 +498,10 @@ STEP = '-'
rectangle[x][y] = self.REASON_DRAWING
if self.debug:
print("Post Drawnings:")
wxPrint("Post Drawnings:")
self.PrintRect(rectangle)
print ("Remove vias to guarantee step size...")
wxPrint ("Remove vias to guarantee step size...")
clear_distance = 0
if self.step != 0.0:
clear_distance = int((self.step+l_clearance) / l_clearance) # How much "via steps" should be removed around a via (round up)
@ -507,14 +523,14 @@ STEP = '-'
self.AddVia(wxPoint(via.PosX + ran_x, via.PosY + ran_y), via.X, via.Y)
if self.debug:
print("\nFinal result:")
wxPrint("\nFinal result:")
self.PrintRect(rectangle)
self.RefillBoardAreas()
if self.filename:
self.pcb.Save(self.filename)
print ("Done!")
wxPrint ("Done!")
if __name__ == '__main__':
if len(sys.argv) < 2: