test/kicad-action-scripts
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Allow ViaStitching working on kicad 5.1

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This commit is contained in:
Jean-Samuel Reynaud
2019-04-19 18:19:08 +02:00
parent f65c507ddc
commit 43116af07c
1 changed files with 53 additions and 48 deletions
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27
ViaStitching/FillArea.py
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@ -113,7 +113,7 @@ class FillArea:
break break
self.netname = None self.netname = None
self.debug = False self.debug = False
self.random = False self.random = True
self.star = False self.star = False
if self.netname is None: if self.netname is None:
self.SetNetname("GND") self.SetNetname("GND")
@ -126,6 +126,7 @@ class FillArea:
self.SetPCB(LoadBoard(self.filename)) self.SetPCB(LoadBoard(self.filename))
def SetDebug(self): def SetDebug(self):
print("Set debug")
self.debug = True self.debug = True
return self return self
@ -221,7 +222,8 @@ STEP = '-'
m.SetViaType(VIA_THROUGH) m.SetViaType(VIA_THROUGH)
m.SetDrill(int(self.drill)) m.SetDrill(int(self.drill))
m.SetWidth(int(self.size)) m.SetWidth(int(self.size))
m.SetTimeStamp(33) # USE 33 as timestamp to mark this via as generated # No more possible to mark via as own since no timestamp_t binding
#m.SetTimeStamp(33) # USE 33 as timestamp to mark this via as generated
self.pcb.Add(m) self.pcb.Add(m)
def RefillBoardAreas(self): def RefillBoardAreas(self):
@ -229,8 +231,8 @@ STEP = '-'
area = self.pcb.GetArea(i) area = self.pcb.GetArea(i)
area.ClearFilledPolysList() area.ClearFilledPolysList()
area.UnFill() area.UnFill()
if not area.GetIsKeepout(): filler = ZONE_FILLER(self.pcb);
area.BuildFilledSolidAreasPolygons(self.pcb) filler.Fill(self.pcb.Zones())
def CheckViaInAllAreas(self, via, all_areas): def CheckViaInAllAreas(self, via, all_areas):
''' '''
@ -313,14 +315,17 @@ STEP = '-'
""" """
Launch the process Launch the process
""" """
target_tracks = self.pcb.GetTracks()
if self.delete_vias: if self.delete_vias:
target_tracks = filter(lambda x: (x.GetNetname().upper() == self.netname), self.pcb.GetTracks()) # timestmap no more available
for via in target_tracks: # target_tracks = filter(lambda x: (x.GetNetname().upper() == self.netname), self.pcb.GetTracks())
if via.Type() == PCB_VIA_T: # for via in target_tracks:
if via.GetTimeStamp() == 33: # pprint.pprint(via.GetTimeStamp())
self.pcb.RemoveNative(via) # if via.Type() == PCB_VIA_T:
self.RefillBoardAreas() # if via.GetTimeStamp() == 33:
# self.pcb.RemoveNative(via)
# self.RefillBoardAreas()
return # no need to run the rest of logic return # no need to run the rest of logic
lboard = self.pcb.ComputeBoundingBox(True) lboard = self.pcb.ComputeBoundingBox(True)
@ -366,7 +371,7 @@ STEP = '-'
for dy in [-offset, offset]: # All 4 corners of the via are testet (upper, lower, left, right) but not the center for dy in [-offset, offset]: # All 4 corners of the via are testet (upper, lower, left, right) but not the center
point_to_test = wxPoint(current_x + dx, current_y + dy) point_to_test = wxPoint(current_x + dx, current_y + dy)
hit_test_area = area.HitTestFilledArea(point_to_test) # Collides with a filled area hit_test_area = area.HitTestFilledArea(point_to_test) # Collides with a filled area
hit_test_edge = area.HitTestForEdge(point_to_test) # Collides with an edge/corner hit_test_edge = area.HitTestForEdge(point_to_test,area_clearance) # Collides with an edge/corner
test_result &= (hit_test_area and not hit_test_edge) # test_result only remains true if the via is inside an area and not on an edge test_result &= (hit_test_area and not hit_test_edge) # test_result only remains true if the via is inside an area and not on an edge