diff --git a/ViaStitching/FillArea.py b/ViaStitching/FillArea.py
index d80f6b4..1c716b2 100644
--- a/ViaStitching/FillArea.py
+++ b/ViaStitching/FillArea.py
@@ -349,11 +349,12 @@ STEP         = '-'
             # timestmap again available
             #target_tracks = filter(lambda x: (x.GetNetname().upper() == self.netname), self.pcb.GetTracks())
             target_tracks = filter(lambda x: (x.GetNetname() == self.netname), self.pcb.GetTracks())
-            for via in target_tracks:
-                # pprint.pprint(via.GetTimeStamp())
-                if via.Type() == PCB_VIA_T:
-                    if via.GetTimeStamp() == 33:
-                        self.pcb.RemoveNative(via)
+            target_tracks_cp = list(target_tracks)
+            l = len (target_tracks_cp)
+            for i in range(l):
+                if target_tracks_cp[i].Type() == PCB_VIA_T:
+                    if target_tracks_cp[i].GetTimeStamp() == 33:
+                        self.pcb.RemoveNative(target_tracks_cp[i])
             self.RefillBoardAreas()
             return                                          # no need to run the rest of logic
 
diff --git a/ViaStitching/FillAreaAction.py b/ViaStitching/FillAreaAction.py
index 1183b0d..c97b851 100644
--- a/ViaStitching/FillAreaAction.py
+++ b/ViaStitching/FillAreaAction.py
@@ -71,7 +71,7 @@ class FillAreaAction(pcbnew.ActionPlugin):
         PopulateNets("GND", a)
         modal_result = a.ShowModal()
         if modal_result == wx.ID_OK:
-            wx.LogMessage('Via Stitching: Version 1.4')
+            wx.LogMessage('Via Stitching: Version 1.5')
             if 1:  # try:
                 fill = FillArea.FillArea()
                 fill.SetStepMM(float(a.m_StepMM.GetValue().replace(',', '.')))